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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16603-1E
32-bit Microcontroller
CMOS
FR60 MB91460R Series
MB91F467R
DESCRIPTION
MB91460R series is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control applications such as consumer devices and vehicle system, which require high-speed real-time processing. MB91460R series uses the FR60 CPU compatible with the FR family* CPUs. MB91460R series contains the LIN-UART and CAN controller. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURES
* FR60 CPU * 32-bit RISC, load/store architecture, five-stage pipeline * Maximum operating frequency : 80 MHz (oscillation frequency 20 MHz, oscillation frequency 4 multiplier (PLL clock multiplication method)) * 16-bit fixed-length instructions (basic instructions) * Instruction execution speed : 1 instruction per cycle * Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions: Instructions suitable for embedded applications * Function entry/exit instructions and register data multi load store instructions: Instructions supporting C language * Register interlock function : Facilitating assembly-language coding * Built-in multiplier with instruction-level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (PC/PS saving) : 6 cycles (16 priority levels) (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB91460R Series
* Harvard architecture enabling simultaneous execution of both program access and data access * Instructions compatible with the FR family * Internal peripheral resources * Flash memory capacity : 1088 bytes * Internal RAM capacity : 0 Wait access 16 Kbytes + 1 Wait access 32 Kbytes + 16 Kbytes (Instruction/data common RAM) * General-purpose port : Maximum 138 ports * DMAC (DMA Controller) Maximum of 5 channels for simultaneous operation is possible. (1 channel for external-to-external) 3 transfer sources (external pin/internal peripheral/software) Activation source can be selected using software. Addressing mode with 32-bit full address indication (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Fly-by transfer support (between external I/O and memory) Transfer data size selection 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) * A/D converter (sequential comparison) 10-bit resolution: 16 channels Conversion time: 3 s (peripheral macro operation clock at 16.67 MHz) * External interrupt input: 16 channels Pins shared with RX pins of CAN0 and CAN1 * Bit search module (for REALOS) Function of searching for the first "0" data/ "1" data/change bit position in 1 word from the MSB (upper bit) * LIN-USART (full duplex double buffer): 7 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator * I2C* bus interface (400 kbps supported): 3 channels Master/slave sending and receiving Arbitration function, clock synchronization function * CAN controller (C-CAN) : 2 channels Maximum transfer speed : 1 Mbps 32 sent/received message buffers * 16-bit PPG timer : 8 channels * 16-bit reload timer : 5 channels * 16-bit free-run timer : 4 channels (1 channel each for ICU and OCU) * Input capture : 4 channels (work with free-run timer) * Output compare : 4 channels (work with free-run timer) * Watchdog timer Watchdog reset output pin available * Real-time clock * Low-power consumption mode: Sleep/stop/shutdown mode function * Clock modulator * Sub clock calibration * Main oscillation stabilization wait timer * Sub oscillation stabilization wait timer (Continued) 2
MB91460R Series
(Continued) * Package : LQFP-176 (FPT-176P-M07) * CMOS 0.18 m technology * 3 V/5 V power supplies [Internal logic is kept at 1.8 V by step-down circuit, some I/Os have the withstand voltage of 5.0 V] * Operating temperature range : between - 40C and + 85C * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
3
MB91460R Series
PIN ASSIGNMENT
(TOP VIEW)
176 VCO5 175 P17_3/PPG3 174 P17_2/PPG2 173 P17_1/PPG1 172 P17_0/PPG0 171 P14_3/ICU3/TIN3/TRG3 170 P14_2/ICU2/TIN2/TRG2 169 P14_1/ICU1/TIN1/TRG1 168 P14_0/ICU0/TIN0/TRG0 167 P22_3 166 P22_2/INT13 165 P22_0/INT12 164 P23_6/INT11 163 P23_4/INT10 162 VCC5 161 VSS 160 P15_3/OCU3/TOT3 159 P15_2/OCU2/TOT2 158 P15_1/OCU1/TOT1 157 P15_0/OCU0/TOT0 156 P18_2/SCK6 155 P18_1/SOT6 154 P18_0/SIN6 153 P19_6/SCK5 152 P19_5/SOT5 151 P19_4/SIN5 150 P19_2/SCK4 149 P19_1/SOT4 148 P19_0/SIN4 147 VCC5 146 VSS 145 P20_6/SCK3/FRCK3 144 P20_5/SOT3 143 P20_4/SIN3 142 P20_2/SCK2/FRCK2 141 P20_1/SOT2 140 P20_0/SIN2 139 P21_6/SCK1/FRCK1 138 P21_5/SOT1 137 P21_4/SIN1 136 P21_2/SCK0/FRCK0 135 P21_1/SOT0 134 P21_0/SIN0 133 VCC5 VSS P24_2/INT2 P24_3/INT3 P22_6/SDA1/INT15 P22_7/SCL1 P24_4/SDA2/INT4 P24_5/SCL2/INT5 P13_0/DREQ0 P13_1/DACK0 P13_2/DEOP0 VCC3 VCC3 VSS C_1 P09_4/CS4 P09_3/CS3 P09_2/CS2 P09_1/CS1 P09_0/CS0 P11_0/IORD P11_1/IOWR P08_7/RDY P08_6/BRQ P08_5/BGRNT P08_4/RD P08_1/WR1 P08_0/WR0 NMI P10_6/MCLKE P10_5/MCLKI P10_4/MCLKO P10_3/WE P10_2/BAA P10_1/AS P10_0/SYSCLK VCC3 C_2 VSS X0 X1 VSS X0A X1A VCC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 (1) (2) (3)
LQFP-176
132 VSS 131 INIT 130 MD0 129 MD1 128 MD2 127 MD3 126 P23_3/TX1 125 P23_2/RX1/INT9 124 P23_1/TX0 123 P23_0/RX0/INT8 122 P24_7/INT7 121 P24_6/INT6 120 P24_1/INT1 119 P24_0/INT0 118 P22_5/SCL0 117 P22_4/SDA0/INT14 116 AVRH 115 AVCC3 114 AVSS/AVRL 113 P28_7/AN15 112 P28_6/AN14 111 P28_5/AN13 110 P28_4/AN12 109 P28_3/AN11 108 P28_2/AN10 107 P28_1/AN9 106 P28_0/AN8 105 P29_7/AN7 104 P29_6/AN6 103 P29_5/AN5 102 P29_4/AN4 101 P29_3/AN3 100 P29_2/AN2 99 P29_1/AN1 98 P29_0/AN0 97 WDRESET 96 P17_7/PPG7 95 P17_6/PPG6 94 P17_5/PPG5 93 P17_4/PPG4 92 P16_7/ATG 91 P05_7/A23 90 P05_6/A22 89 VCC3
Note : (1) to (3) are 3.3 V/5 V pin supported pin, and can set 3.3 V and 5 V to the voltage in each block. I2C pin in (1) can be inputted at 5 V power supply. However, 3.3 V of the input threshold value is used as the standard value regardless of the power supply voltage. If 5 V is set in (1) or (2), also set 5 V to (3).
4
VSS P01_0/D16 P01_1/D17 P01_2/D18 P01_3/D19 P01_4/D20 P01_5/D21 P01_6/D22 P01_7/D23 P00_0/D24 P00_1/D25 P00_2/D26 VCC3 VSS P00_3/D27 P00_4/D28 P00_5/D29 P00_6/D30 P00_7/D31 P07_0/A00 P07_1/A01 P07_2/A02 P07_3/A03 P07_4/A04 P07_5/A05 P07_6/A06 P07_7/A07 P06_0/A08 VCC3 VSS P06_1/A09 P06_2/A10 P06_3/A11 P06_4/A12 P06_5/A13 P06_6/A14 P06_7/A15 P05_0/A16 P05_1/A17 P05_2/A18 P05_3/A19 P05_4/A20 P05_5/A21 VSS
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
(FPT-176P-M07)
MB91460R Series
PIN DESCRIPTION
Pin no. Pin name P24_2 INT2 P24_3 INT3 P22_6 4 SDA1 INT15 P22_7 5 SCL1 P24_4 6 SDA2 INT4 P24_5 7 SCL2 INT5 8 9 10 15 16 17 18 19 20 P13_0 DREQ0 P13_1 DACK0 P13_2 DEOP0 P09_4 CS4 P09_3 CS3 P09_2 CS2 P09_1 CS1 P09_0 CS0 P11_0 IORD I/O I/O circuit type* D D Description General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port C I2C bus DATA input/output pin External interrupt input pin General-purpose input/output port C I2C bus Clock input/output pin General-purpose input/output port C I2C bus DATA input/output pin External interrupt input pin General-purpose input/output port C I2C bus Clock input/output pin External interrupt input pin H H H H H H H H H General-purpose input/output port DMA external transfer request input pin General-purpose input/output port DMA external transfer acknowledgement output pin General-purpose input/output port DMA external transfer EOP (End of Process) output pin General-purpose input/output port Chip select 4 output pin General-purpose input/output port Chip select 3 output pin General-purpose input/output port Chip select 2 output pin General-purpose input/output port Chip select 1 output pin General-purpose input/output port Chip select 0 output pin General-purpose input/output port Read strobe output pin at DMA flyby transfer (Continued) 5
2 3
I/O I/O I/O Open Drain I/O Open Drain I/O Open Drain I/O Open Drain I/O I/O I/O I/O I/O I/O I/O I/O I/O
MB91460R Series
Pin no.
Pin name P11_1 IOWR P08_7 RDY P08_6 BRQ P08_5 BGRNT P08_4 RD P08_1
I/O
I/O circuit type* H H H H H
Description General-purpose input/output port Write strobe output pin at DMA flyby transfer General-purpose input/output port External ready input pin General-purpose input/output port External bus release request input pin General-purpose input/output port External bus release reception output pin General-purpose input/output port External read strobe output pin General-purpose input/output port External write strobe output pin (DQMU signal when using SDRAM) General-purpose input/output port (DQML signal when using SDRAM) External write strobe output pin NMI (Non Maskable Interrupt) input pin General-purpose input/output port Clock enable output signal pin for SDRAM General-purpose input/output port Clock input pin for SDRAM General-purpose input/output port Clock output pin for SDRAM General-purpose input/output port External write enable signal pin General-purpose input/output port Address advance output pin for burst mode FLASH memory General-purpose input/output port Address strobe output pin General-purpose input/output port System clock output pin Clock (oscillation) input pin Clock (oscillation) output pin Sub lock (oscillation) input pin Sub lock (oscillation) output pin
21 22 23 24 25
I/O I/O I/O I/O I/O
26
WR1 P08_0 WR0
I/O
H
27 28 29 30 31 32
I/O I I/O I/O I/O I/O
H H H H H H
NMI P10_6 MCLKE P10_5 MCLKI P10_4 MCLKO P10_3 WE P10_2
33
BAA P10_1 AS P10_0 SYSCLK X0 X1 X0A X1A
I/O
H
34 35 39 40 42 43 6
I/O I/O
H H G G G G
MB91460R Series
(Continued) I/O circuit type* H H H H H H H I F F
Pin no.
Pin name P01_0 to P01_7 D16 to D23
I/O
Description General-purpose input/output ports External data buses (D16 to D23) General-purpose input/output ports External data buses (D24 to D31) General-purpose input/output ports External address buses (A00 to A07) General-purpose input/output ports External address buses (A08 to A15) General-purpose input/output ports External address buses (A16 to A23) General-purpose input/output ports A/D converter external trigger input General-purpose input/output ports PPG timer output pin Watchdog reset output pin General-purpose input/output ports Analog input pins for A/D converter General-purpose input/output ports Analog input pins for A/D converter General-purpose input/output port I2C bus DATA input/output pin External interrupt input pin General-purpose input/output port
46 to 53
I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O Open Drain I/O Open Drain
54 to 56 P00_0 to P00_7 59 to 63 D24 to D31 64 to 71 P07_0 to P07_7 A00 to A07
P06_0 to P06_7 72 76 to 81 A08 to A15 82 to 87 P05_0 to P05_7 90, 91 A16 to A23 92 93 to 96 97 98 to 105 106 to 113 P16_7 ATG P17_4 to P17_7 PPG4 to PPG7 WDRESET P29_0 to P29_7 AN0 to AN7 P28_0 to P28_7 AN8 to AN15 P22_4 117 SDA0 INT14 P22_5 118 SCL0 P24_0, P24_1 119, 120 INT0, INT1 P24_6 121 INT6 P24_7 122 INT7
C
C
I2C bus clock input/output pin General-purpose input/output ports
I/O
D
External interrupt input pins Can be used as a source for recovering from shutdown General-purpose input/output port External interrupt input pin Can be used as a source for recovering from shutdown General-purpose input/output port External interrupt input pin Can be used as a source for recovering from shutdown (Continued) 7
I/O
D
I/O
D
MB91460R Series
Pin no.
Pin name P23_0
I/O
I/O circuit type*
Description General-purpose input/output port
123
RX0 INT8
I/O
D
RX input/output pin of CAN0 External interrupt input pin Can be used as a source for recovering from shutdown
124
P23_1 TX0 P23_2 RX1 INT9
I/O
D
General-purpose input/output port TX output pin of CAN0 General-purpose input/output port RX input/output pin of CAN1 External interrupt input pin Can be used as a source for recovering from shutdown
125
I/O
D
126 127 128 129 130 131 134 135
P23_3 TX1 MD3 MD2 MD1 MD0 INIT P21_0 SIN0 P21_1 SOT0 P21_2 SCK0 FRCK0 P21_4 SIN1 P21_5 SOT1 P21_6 SCK1 FRCK1 P20_0 SIN2 P20_1 SOT2
I/O I I I I I I/O I/O
D A J J J B D D
General-purpose input/output port TX output pin of CAN0
Mode setting pins
External reset input pin General-purpose input/output port Data input pin of UART0 General-purpose input/output port Data output pin of UART0 General-purpose input/output port Clock input/output pin of UART0 External clock input pin of free-run timer0 General-purpose input/output port Data input pin of UART1 General-purpose input/output port Data output pin of UART1 General-purpose input/output port Clock input/output pin of UART1 External clock input pin of free-run timer 1 General-purpose input/output port Data input pin of UART2 General-purpose input/output port Data output pin of UART2 (Continued)
136
I/O
D
137 138
I/O I/O
D D
139
I/O
D
140 141
I/O I/O
D D
8
MB91460R Series
Pin no.
Pin name P20_2
I/O
I/O circuit type* D
Description General-purpose input/output port
142
SCK2 FRCK2 P20_4 SIN3 P20_5 SOT3 P20_6 SCK3 FRCK3 P19_0 SIN4 P19_1 SOT4 P19_2 SCK4 P19_4 SIN5 P19_5 SOT5 P19_6 SCK5 P18_0 SIN6 P18_1 SOT6 P18_2 SCK6 P15_0 to P15_3 OCU0 to OCU3 TOT0 to TOT3 P23_4 INT10 P23_6 INT11
I/O
Clock input/output pin of UART2 External clock input pin of free-run timer 2 General-purpose input/output port Data input pin of UART3 General-purpose input/output port Data output pin of UART3 General-purpose input/output port Clock input pin of UART3 External clock input pin of free-run timer 3 General-purpose input/output port Data input pin of UART4 General-purpose input/output port Data output pin of UART4 General-purpose input/output port Clock input/output pin of UART4 General-purpose input/output port Data input pin of UART5 General-purpose input/output port Data output pin of UART5 General-purpose input/output port Clock input/output pin of UART5 General-purpose input/output port Data input pin of UART6 General-purpose input/output port Data output pin of UART6 General-purpose input/output port Clock input/output pin of UART6 General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin (Continued) 9
143 144
I/O I/O
D D
145
I/O
D
148 149 150 151 152 153 154 155 156
I/O I/O I/O I/O I/O I/O I/O I/O I/O
D D D D D D D D D
157 to 160
I/O
D
163 164
I/O I/O
D D
MB91460R Series
(Continued) Pin no. Pin name P22_0 INT12 P22_2 INT13 P22_3 P14_0 to P14_3 168 to 171 ICU0 to ICU3 TIN0 to TIN3 TRG0 to TRG3 172 to 175 P17_0 to P17_3 PPG0 to PPG3 I/O D I/O D I/O I/O circuit type* D D D Description General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG General-purpose input/output ports PPG timer output pins
165 166 167
I/O I/O I/O
* : For I/O circuit type, refer to " I/O CIRCUIT TYPE".
10
MB91460R Series
[Power supply/GND pins] Pin number Pin name 1, 13, 38, 41, 45, 58, 74, 88, 132, 146, 161 11, 12, 36, 44, 57, 73, 89 VSS VCC3
I/O (VSS) (VCC3) GND pins 3.3 V power supply pins
Function
133, 147
VCC5
(VCC5)
5 V power supply pins. These pins are I/O power supplies corresponding to 117 to 145 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5 V when supplying 5V. Be sure to supply 5 V if more than one 5V operating pin is specified, or 5V is supplied at pin 162 or pin 176. 5 V power supply pin. This pin is an I/O power supply corresponding to 148 to 160 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5V when supplying 5 V. Be sure to supply 5 V if more than one 5 V operating pin is specified. 5 V power supply pin. This pin is an I/O power supply corresponding to 2 to 7 pins. The corresponding I/O pin operates at 3.3 V when supplying 3.3 V, and at 5 V when supplying 5 V. Be sure to supply 5 V if more than one 5 V operating pin is specified. Analog GND pin for A/D converter 3.3 V power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator Connect to a capacitance of 4.7 F. Capacitor connection pin for internal regulator Connect to a capacitance of 4.7 F.
162
VCC5
(VCC5)
176
VCC5
(VCC5)
114 115 116 14 37
AVSS/ AVRL AVCC3 AVRH C_1 C_2
(AVSS) (AVCC3) (AVRH)
11
MB91460R Series
I/O CIRCUIT TYPE
Type 5 V level A
N-ch
Circuit type
Remarks 5 V CMOS hysteresis input With 50 k pull-down
Input
Pull-down
5 V CMOS hysteresis input With 50 k pull-up
P-ch Pull-up
B Input 5 V level I/O pin for I2C Withstand voltage of 5 V (with standby control)
N-ch
Output driving N-ch Input Standby control
C
P-ch
Pull-up control
P-ch N-ch
5 V level
Output driving P-ch Output driving N-ch Pull-down control Input Standby control Input Standby control
5 V CMOS output 5 V CMOS input 5 V CMOS hysteresis level input With pull-up/pull-down control (with standby control)
D
N-ch
(Continued)
12
MB91460R Series
Type
Circuit type
Remarks 3.3 V CMOS output 3.3 V CMOS input 3.3 V CMOS hysteresis level input Analog input (with standby control)
3.3 V level
P-ch N-ch
Output driving P-ch Output driving N-ch Input Standby control Input Standby control Analog input
F
3.3 V level Input G
3.3 V oscillation cell
Standby control 3.3 V CMOS output 3.3 V CMOS input 3.3 V CMOS hysteresis level input With pull-up/pull-down control (with standby control)
P-ch
Pull-up control
P-ch N-ch
3.3 V level
Output driving P-ch Output driving N-ch Pull-down control Input Standby control Input Standby control
H
N-ch
(Continued)
13
MB91460R Series
(Continued) Type 3.3 V level
P-ch
Circuit type
Remarks 3.3 V CMOS output
Output driving P-ch Output driving N-ch
I
N-ch
5 V level J Input
5 V CMOS hysteresis input
14
MB91460R Series
HANDLING DEVICES
* Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output pin or if a voltage exceeding the rating is applied between VCC5 pin (VCC3 pin) and VSS pin. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, when using a CMOS IC, do not exceed the maximum rating. * Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor. * Power supply pins In MB91460R series, devices including multiple VCC5 pin (VCC3 pin) and VSS pin are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pin and GND pin must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the VCC5 pin (VCC3 pin) pins and VSS pin of the MB91460R series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between VCC5 pin (VCC3 pin) and VSS pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 F to C_1 and C_2 pins for the regulator. * Crystal oscillator circuit Noise in proximity to the X0 and X1 (X0A, X1A) pins can cause abnormal operation in this device. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are placed as close together as possible. The use of printed circuit board architecture in which the X0 and X1 (X0A, X1A) pins are surrounded by ground contributes to stable operation and is strongly recommended. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Notes on using external clock In principle, when using external clock, supply a clock to the X0 pin and X1 pin simultaneously. Also, an opposite phase clock to the X0 pin must be supplied to the X1 pin. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1 pin stops at "H" output in STOP mode).
X0 X1
(Note) Stop mode (oscillation stop mode) cannot be used. Example of using external clock (normal)
15
MB91460R Series
* Mode pins (MD0 to MD3) When using mode pins, connect them directly to VCC5 pin (VCC3 pin) or VSS pin. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and VCC5 pin (VCC3 pin) or VSS pin on the printed circuit board as possible and connect them with low impedance. * Power-on sequences for 3.3 V and 5 V * Immediately after power-on, keep "L" level input to the INIT pin for the oscillation stabilization wait time (8 ms) to ensure the oscillation stabilization wait time for the oscillator circuit. * There is no power-on sequences. * When executing a reset cancellation (changing INIT pin from "L" level to "H" level), be sure to execute it while 3 V and 5 V power supplies are stable. * Caution on operations during PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. * External bus setting This model guarantees the maximum frequency of 40 MHz for the external bus clock SYSCLK. Setting the base clock frequency to 80 MHz without changing the initial value of DIVR1 (external bus base clock division setting register) sets the external bus frequency also to 80 MHz. Before changing the base clock frequency, set SYSCLK not exceeding 40 MHz. * Pull-up control Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC standard. * Notes on PS register Since some instructions process the PS register in advance, the exceptional operations may cause a break in the interrupt process routine or an update of display contents of the flag in the PS register when the debugger is being used. In either case, as the device is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified. 1) The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction accepts a user interrupt/NMI, executes a step, or breaks in response to a data event or emulator menu. -D0 and D1 flags are updated in advance. -An EIT process routine (user interrupt/NMI or emulator) is executed. -Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1). 2) The following operations are performed when each instruction of OR CCR, ST ILM, MOV Ri and PS is executed to enable interrupts while a user interrupt/NMI source has been occurring. -The PS register is updated in advance. -An EIT process routine (user interrupt/NMI or emulator) is executed. -Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as that in 1).
16
MB91460R Series
NOTES ON DEBUGGER
* Step execution of RETI instruction In the environment where interrupts occur frequently when stepping, only the corresponding interrupt process routines are repeated. As the result of that, the main routine and low-interrupt-level programs are not executed (For example, if an interrupt to the time base timer is enabled, a break always occurs at the beginning of the time base routine when stepping RETI) . Disable the corresponding interrupts when the debug on the corresponding interrupt process routines becomes unnecessary. * Break function If the target address of a hardware break (including an event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after execution of one instruction even though there is no actual data access instruction in the user program. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of a hardware break (including an event break). * Operand break If a stack pointer exists in the area which is set as the DSU operand break, malfunctions may occur. Do not set the access to the areas containing the address of system stack pointer as a target of data event break.
17
MB91460R Series
BLOCK DIAGRAM
FR60 CPU Core
EDSU/MPU
Bit search
RAM 16 Kbytes (0 wait) + 32 Kbytes (1 wait)
I-bus 32
D-bus 32
CAN (2 channels) 32 16 Bus adapter
RX0,RX1 TX0,TX1 SYSCLK AS RD WR0 WR1 MCLKE MCLKI MCLKO WE BAA BRQ BGRNT CS0 to CS4 A23 to A00 D31 to D16
Direct mapped cache 8 Kbytes
Flash ROM 1088 bytes RAM 16 Kbytes
Bus Converter
External bus interface
DREQ0 DACK0 DEOP0 IOWR IORD
DMAC (5 channels)
R-bus 16
Interrupt controller Clock control
TRG0 to TRG3 PPG0 to PPG7 TIN0 to TIN3 TOT0 to TOT3
External interrupt (16 channels)
PPG (8 channels) Reload Timer (5 channels) Free-run Timer (4 channels) Input Capture (4 channels)
Output Compare (4 channels)
NMI INT0 to INT15
PORT interface
LIN-USART (7 channels) (including BRG)
PORT
SIN0 to SIN6 SOT0 to SOT6 SCK0 to SCK6 SDA0 to SDA2 SCL0 to SCL2
FRCK0 to FRCK3
I2C (3 channels) RTC
ICU0 to ICU3
OCU0 to OCU3
A/D converter (16 channels)
AN0 to AN15 ATG
18
MB91460R Series
CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications.
1. Features
* Adoption of RISC architecture Basic instruction : 1 instruction per cycle * General-purpose registers : 32-bit x 16 registers * Linear memory space : 4 Gbytes * Multiplier installed 32-bit x 32-bit multiplication 5 cycles 16-bit x 16-bit multiplication 3 cycles * Enhanced interrupt processing function - Quick response speed (6 cycles) - Multiple-interrupt support - Level mask function (16 levels) * Enhanced instructions for I/O operation - Memory-to-memory transfer instructions - Bit processing instructions * Basic instruction word length 16 bits * Low-power consumption Sleep mode/stop mode/shutdown mode
19
MB91460R Series
2. Internal architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. A 32-bit 16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. A Harvard Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. The following figure shows the internal architecture structure.
DSU (debug support)
FR60 CPU core Bit search
Instruction cache RAM
I-bus 32 D-bus 32
CAN (2 channels) 32 16 bus adapter
RAM 16 Kbytes
Bus converter
R-bus 16
External bus interface
DMAC (5 channels) Peripheral resource
20
MB91460R Series
3. Programming model
* Basic programming model 32 bits Initial value
R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H
General-purpose registers
R12 R13 R14 R15
Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiply and divide result registers
PC RS TBR RP SSP USP MDH MDL ILM SCR CCR
21
MB91460R Series
4. Registers
* General-purpose register
32 bits Initial value
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). * PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always "0". Write access to these bits is invalid. Bit position bit 31
bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
22
MB91460R Series
* CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
- - 00XXXXB
S
I
N
Z
V
C
S I Z V
: Stack flag : Interrupt enable flag : Zero flag : Overflow flag
N : Negative enable flag
C : Carry flag * SCR (System Condition Register)
bit 10 bit 9 bit 8
Initial value
XX0B
D1
D0
T
Flag for step multiplication (D1, D0) This flag stores interim data during execution of step multiplication. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. * ILM
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
01111B
ILM4 ILM3 ILM2 ILM1 ILM0
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value "01111B" at reset. * PC (Program Counter)
bit 31 bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined.
23
MB91460R Series
* TBR (Table Base Register)
bit 31 bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. * RP (Return Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. * USP (User Stack Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is "1", this register functions as the R15 register. * The USP register can also be explicitly specified. The initial value at reset is undefined. * This register cannot be used with RETI instructions. * Multiply & divide registers
bit 31 MDH MDL bit 0
These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined.
24
MB91460R Series
MODE SETTING
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode.
1. Mode pins
The three pins MD2, MD1, MD0 are used to specify the mode vector fetch related settings. Settings other than shown in the table are not allowed. Mode pins* Reset vector Mode name access area MD2 MD1 MD0 0 0 0 0 0 1 Internal ROM mode vector External ROM mode vector Internal External Bus width is set by mode register.
Remarks
* : Always use MD3 with "0". Note : The FR family does not support the external mode vector fetch using multiplex bus.
2. Mode register (MODR)
The data written to the mode register using mode vector fetch is called mode data. After the mode register (MODR) is set, the device operates according to the operation mode set in this register. The mode register is set by all reset sources. User programs cannot write data to the mode register. Rewriting is allowed in the emulator mode. In this case, use an 8-bit length data transfer instruction. A 16/32-bit length transfer instruction cannot be used for writing. Description of the mode register is given below. [Mode register description]
bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 ROMA bit 1 WTH1 bit 0 WTH0
Initial value
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits Be sure to set these bits to "00000B". Operation is not guaranteed when any value other than "00000B" is set. [bit2] ROMA (Internal enable bit) The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas. ROMA Function Remarks 0 1 External ROM mode Internal ROM mode Internal F-bus RAM becomes valid. The internal ROM area (40000H to FFFFFH) is used as an external area. Internal F-bus RAM and F-bus ROM become valid.
25
MB91460R Series
[bit1, bit0] WTH1, WTH0 (Bus width setting bits) These bits are used to set the bus width to be used in the external bus mode. When the operation mode is the external bus mode, these values are set in bits BW1 and BW0 in AMD0 (CS0 area). WTH1 WTH0 Function Remarks 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width Single chip mode External bus mode External bus mode Setting disabled Single chip mode
26
MB91460R Series
MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. * Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH
2. Memory map
Internal ROM external bus mode
0000 0000H I/O 0000 0400H I/O 0002 4000H D-bus RAM (1 wait) 0002 C000H 0003 0000H 0003 4000H D-bus RAM (0 wait) F-bus RAM 0003 4000H 0002 C000H 0003 0000H D-bus RAM (0 wait) F-bus RAM 0002 4000H D-bus RAM (1 wait)
External ROM external bus mode Direct addressing area
0000 0000H I/O 0000 0400H I/O
Direct addressing area
0004 0000H
0004 0000H
Flash memory
External area
0015 0000H
External area*
FFFF FFFFH FFFF FFFFH
* : The region from 150000H may not be able to be used as an external region, depending on the CS region setting.
27
MB91460R Series
I/O MAP
Address 000000H Register +0 PDR0 [R/W]B XXXXXXXX +1 PDR1 [R/W]B XXXXXXXX +2 PDR2 [R/W]B XXXXXXXX +3 PDR3 [R/W]B XXXXXXXX Block T-unit port data register
Read/write attribute, Access unit (B: Byte, H: Half word, W: Word) Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows: " 1 " : Initial value " 1 " " 0 " : Initial value " 0 " " X " : Initial value " undefined " " - " : No physical register at this location " * " : The same value as value of WTH bit Access is barred with an undefined data access attribute.
28
MB91460R Series
Address
Register +0 PDR00 [R/W] B, H XXXXXXXX Reserved PDR08 [R/W] B, H XXXX - - XX Reserved PDR16 [R/W] B, H X------PDR20 [R/W] B, H - XXX - XXX PDR24 [R/W] B, H XXXXXXXX PDR28 [R/W] B, H XXXXXXXX PDR29 [R/W] B, H XXXXXXXX Reserved +1 PDR01 [R/W] B, H XXXXXXXX PDR05 [R/W] B, H XXXXXXXX PDR09 [R/W] B, H - - - XXXXX PDR13 [R/W] B, H - - - - - XXX PDR17 [R/W] B, H XXXXXXXX PDR21 [R/W] B, H - XXX - XXX +2 Reserved PDR06 [R/W] B, H XXXXXXXX PDR10 [R/W] B, H - XXXXXXX PDR14 [R/W] B, H - - - - XXXX PDR18 [R/W] B, H - - - - - XXX PDR22 [R/W] B, H XXXXXX - X Reserved PDR07 [R/W] B, H XXXXXXXX PDR11 [R/W] B, H - - - - - - XX PDR15 [R/W] B, H - - - - XXXX PDR19 [R/W] B, H - XXX - XXX PDR23 [R/W] B, H - X - XXXXX +3
Block
000000H
000004H
000008H
00000CH
Port Data Register
000010H
000014H
000018H
00001CH 000020H to 00002CH 000030H
Reserved
Reserved External Interrupt (INT 0 to INT 7) NMI External Interrupt (INT 8 to INT 15) DLYI/I-unit Reserved RDR00/TDR00 [R/W] B, H, W 00000000
EIRR0 [R/W] B 00000000 EIRR1 [R/W] B 00000000 DICR [R/W] B -------0
ENIR0 [R/W] B 00000000 ENIR1 [R/W] B 00000000 HRCL [R/W] B 0 - - 11111 Reserved
ELVR0 [R/W] B, H 00000000 00000000 ELVR1 [R/W] B, H 00000000 00000000 Reserved
000034H 000038H 00003CH 000040H
SCR00 [R/W, W] SMR00 [R/W, W] SSR00 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR00 [R/W] B, H 00000X00 ECCR00 [R/W, R, W] B, H -00000XX
LIN-USART 0
000044H
Reserved (Continued)
29
MB91460R Series
Address
Register +0 +1 +2 +3 RDR01/TDR01 [R/W] B, H, W 00000000 SCR01 [R/W, W] SMR01 [R/W, W] SSR01 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR01 [R/W] B, H 00000X00 ECCR01 [R/W, R, W] B, H -00000XX
Block
000048H
LIN-USART 1
00004CH
Reserved RDR02/TDR02 [R/W] B, H, W 00000000
000050H
SCR02 [R/W, W] SMR02 [R/W, W] SSR02 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR02 [R/W] B, H 00000X00 ECCR02 [R/W, R, W] B, H -00000XX
LIN-USART 2
000054H
Reserved RDR03/TDR03 [R/W] B, H, W 00000000
000058H
SCR03 [R/W, W] SMR03 [R/W, W] SSR03 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR03 [R/W] B, H 00000X00 ECCR03 [R/W, R, W] B, H -00000XX
LIN-USART 3
00005CH
Reserved RDR04/TDR04 [R/W] B, H, W 00000000 FCR04 [R/W] B, H 0001 - 000 RDR05/TDR05 [R/W] B, H, W 00000000 FCR05 [R/W] B, H 0001 - 000 RDR06/TDR06 [R/W] B, H, W 00000000 FCR06 [R/W] B, H 0001 - 000
000060H
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR04 [R/W] B, H 00000X00 ECCR04 [R/W, R, W] B, H -00000XX FSR04 [R] B, H - - - 00000
LIN-USART 4 (FIFO)
000064H
000068H
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR05 [R/W] B, H 00000X00 ECCR05 [R/W, R, W] B, H -00000XX FSR05 [R] B, H - - - 00000
LIN-USART 5 (FIFO)
00006CH
000070H
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R] B, H, W B, H, W B, H, W 00000000 00000000 00001000 ESCR06 [R/W] B, H 00000X00 ECCR06 [R/W, R, W] B, H -00000XX FSR06 [R] B, H - - - 00000
LIN-USART 6 (FIFO)
000074H
000078H, 00007CH
Reserved
Reserved (Continued)
30
MB91460R Series
Address
Register +0 BGR100 [R/W] B, H, W 00000000 BGR104 [R/W] B, H, W 00000000 BGR106 [R/W] B, H, W 00000000 BGR102 [R/W] B, H, W 00000000 +1 BGR000 [R/W] B, H, W 00000000 BGR004 [R/W] B, H, W 00000000 BGR006 [R/W] B, H, W 00000000 BGR002 [R/W] B, H, W 00000000 Reserved IBCR0 [R/W] B, H 00000000 ITMKH0 [R/W] B, H 00 - - - - 11 Reserved IBCR1 [R/W] B, H 00000000 ITMKH1 [R/W] B, H 00 - - - - 11 Reserved ITBAH0 [R/W] B, H - - - - - - 00 ISMK0 [R/W] B, H 01111111 ICCR0 [R/W] B - 0011111 ITBAH1 [R/W] B, H - - - - - - 00 ISMK1 [R/W] B, H 01111111 ICCR1 [R/W] B - 0011111 ITBAL0 [R/W] B, H 00000000 ISBA0 [R/W] B, H - 0000000 +2 BGR101 [R/W] B, H, W 00000000 BGR105 [R/W] B, H, W 00000000 BGR107 [R/W] B, H, W 00000000 +3 BGR001 [R/W] B, H, W 00000000 BGR005 [R/W] B, H, W 00000000 BGR007 [R/W] B, H, W 00000000
Block
000080H
000084H
000088H
Baud rate Generator LIN-USART 0 to 6
00008CH 000090H to 0000CCH 0000D0H
Reserved
Reserved
IBSR0 [R] B, H 00000000 ITMKL0 [R/W] B, H 11111111 IDAR0 [R/W] B, H 00000000 IBSR1 [R] B, H 00000000 ITMKL1 [R/W] B, H 11111111 IDAR1 [R/W] B, H 00000000
0000D4H
I2C 0
0000D8H
Reserved ITBAL1 [R/W] B, H 00000000 ISBA1 [R/W] B, H - 0000000 I2C 1
0000DCH
0000E0H
0000E4H 0000E8H to 0000FCH 000100H 000104H 000108H, 00010CH
Reserved
Reserved GCN10 [R/W] B, H 00110010 00010000 GCN11 [R/W] B, H 00110010 00010000 GCN20 [R/W] B - - - - 0000 GCN21 [R/W] B - - - - 0000
Reserved PPG Control 0 to 3 PPG Control 4 to 7 Reserved (Continued) 31
Reserved Reserved Reserved
MB91460R Series
Address 000110H
Register +0 +1 +2 +3 PTMR00 [R] H 11111111 11111111 PDUT00 [W] H XXXXXXXX XXXXXXXX PTMR01 [R] H 11111111 11111111 PDUT01 [W] H XXXXXXXX XXXXXXXX PTMR02 [R] H 11111111 11111111 PDUT02 [W] H XXXXXXXX XXXXXXXX PTMR03 [R] H 11111111 11111111 PDUT03 [W] H XXXXXXXX XXXXXXXX PTMR04 [R] H 11111111 11111111 PDUT04 [W] H XXXXXXXX XXXXXXXX PTMR05 [R] H 11111111 11111111 PDUT05 [W] H XXXXXXXX XXXXXXXX PTMR06 [R] H 11111111 11111111 PDUT06 [W] H XXXXXXXX XXXXXXXX PTMR07 [R] H 11111111 11111111 PDUT07 [W] H XXXXXXXX XXXXXXXX PCSR00 [W] H XXXXXXXX XXXXXXXX PCNH00 [R/W] B, H 0000000 PCNL00 [R/W] B, H 000000 - 0
Block
PPG 0
000114H
000118H
PCSR01 [W] H XXXXXXXX XXXXXXXX PCNH01 [R/W] B, H 0000000 PCNL01 [R/W B, H] 000000 - 0 PPG 1
00011CH
000120H
PCSR02 [W] H XXXXXXXX XXXXXXXX PCNH02 [R/W] B, H 0000000 PCNL02 [R/W] B, H 000000 - 0 PPG 2
000124H
000128H
PCSR03 [W] H XXXXXXXX XXXXXXXX PCNH03 [R/W] B, H 0000000 PCNL03 [R/W] B, H 000000 - 0 PPG 3
00012CH
000130H
PCSR04 [W] H XXXXXXXX XXXXXXXX PCNH04 [R/W] B, H 0000000 PCNL04 [R/W] B, H 000000 - 0 PPG 4
000134H
000138H
PCSR05 [W] H XXXXXXXX XXXXXXXX PCNH05 [R/W] B, H 0000000 PCNL05 [R/W] B, H 000000 - 0 PPG 5
00013CH
000140H
PCSR06 [W] H XXXXXXXX XXXXXXXX PCNH06 [R/W] B, H 0000000 PCNL06 [R/W] B, H 000000 - 0 PPG 6
000144H
000148H
PCSR07 [W] H XXXXXXXX XXXXXXXX PCNH07 [R/W] B, H 0000000 PCNL07 [R/W] B, H 000000 - 0 PPG 7
00014CH
(Continued)
32
MB91460R Series
Address 000170H to 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H 000198H, 00019CH 0001A0H
Register +0 +1 Reserved ICS01 [R/W] B 00000000 ICS23 [R/W] B 00000000 +2 +3
Block
Reserved
Reserved
Reserved
IPCP0 [R] H XXXXXXXX XXXXXXXX IPCP2 [R] H XXXXXXXX XXXXXXXX OCS01 [R/W] H - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] H XXXXXXXX XXXXXXXX OCCP2 [R/W] H XXXXXXXX XXXXXXXX Reserved ADERH [R/W] B, H, W 00000000 00000000 ADCS1 [R/W] B, H 00000000 ADCT1 [R/W] B, H 00010000 Reserved ADCS0 [R/W] B, H 00000000 ADCT0 [R/W] B, H 00101100 ACSR0 [R/W] B, H - 11XXX00
IPCP1 [R] H XXXXXXXX XXXXXXXX IPCP3 [R] H XXXXXXXX XXXXXXXX OCS23 [R/W] H - - - 0 - - 00 0000 - - 00 OCCP1 [R/W] H XXXXXXXX XXXXXXXX OCCP3 [R/W] H XXXXXXXX XXXXXXXX
Input Capture 0 to 3
Output Compare 0 to 3
Reserved ADERL [R/W] B, H, W 00000000 00000000
0001A4
ADCR1 [R] B, H 000000XX ADSCH [R/W] B, H - - - 00000
ADCR0 [R] B, H XXXXXXXX ADECH [R/W] B, H - - - 00000
A/D Converter
0001A8H
0001ACH
Reserved TMR0 [R] H XXXXXXXX XXXXXXXX TMCSRH0 [R/W] B, H - - - 00000 TMCSRL0 [R/W] B, H 0 - 000000
Alarm Comparator 0
0001B0H
TMRLR0 [W] H XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] H XXXXXXXX XXXXXXXX Reserved
0001B4H
Reload Timer 0 (PPG 0, PPG 1)
0001B8H
TMR1 [R] H XXXXXXXX XXXXXXXX TMCSRH1 [R/W] B, H - - - 00000 TMCSRL1 [R/W] B, H 0 - 000000
0001BCH
Reload Timer 1 (PPG 2, PPG 3)
(Continued)
33
MB91460R Series
Address 0001C0H
Register +0 +1 +2 +3 TMRLR2 [W] H XXXXXXXX XXXXXXXX Reserved TMRLR3 [W] H XXXXXXXX XXXXXXXX Reserved TMR2 [R] H XXXXXXXX XXXXXXXX TMCSRH2 [R/W] B, H - - - 00000 TMCSRL2 [R/W] B, H 0 - 000000
Block
0001C4H
Reload Timer 2 (PPG 4, PPG 5)
0001C8H
TMR3 [R] H XXXXXXXX XXXXXXXX TMCSRH3 [R/W] B, H - - - 00000 Reserved TMCSRL3 [R/W] B, H 0 - 000000
0001CCH 0001D0H to 0001E4H 0001E8H
Reload Timer 3 (PPG 6, PPG 7)
Reserved TMR7 [R] H XXXXXXXX XXXXXXXX
TMRLR7 [W] H XXXXXXXX XXXXXXXX Reserved
0001ECH
TMCSRH7 [R/W] B, H - - - 00000 Reserved
TMCSRL7 [R/W] B, H 0 - 000000 TCCS0 [R/W] 00000000 TCCS1 [R/W] 00000000 TCCS2 [R/W] 00000000 TCCS3 [R/W] 00000000
Reload Timer 7 (A/D converter)
0001F0H
TCDT0 [R/W] H XXXXXXXX XXXXXXXX TCDT1 [R/W] H XXXXXXXX XXXXXXXX TCDT2 [R/W] H XXXXXXXX XXXXXXXX TCDT3 [R/W] H XXXXXXXX XXXXXXXX
Free Running Timer 0 (ICU 0, ICU 1) Free Running Timer 1 (ICU 2, ICU 3) Free Running Timer 2 (OCU 0, OCU 1) Free Running Timer 3 (OCU 2, OCU 3)
0001F4H
Reserved
0001F8H
Reserved
0001FCH
Reserved
000200H 000204H 000208H 00020CH 000210H 000214H
DMACA0 [R/W] B, H, W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B, H, W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B, H, W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX (Continued)
DMAC
34
MB91460R Series
Address 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 000364H 000368H
Register +0 +1 +2 +3 DMACA3 [R/W] B, H, W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B, H, W * 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX Reserved DMACR [R/W] B, H, W 00 - - 0000
Block
DMAC
Reserved
Reserved IBCR2 [R/W] B, H 00000000 ITMKH2 [R/W] B, H 00 - - - - 11 Reserved ITBAH2 [R/W] B, H - - - - - - 00 ISMK2 [R/W] B, H 01111111 ICCR2 [R/W] B - 0011111 ITBAL2 [R/W] B, H 00000000 ISBA2 [R/W] B, H - 0000000
Reserved
IBSR2 [R] B, H 00000000 ITMKL2 [R/W] B, H 11111111 IDAR2 [R/W] B, H 00000000
00036CH
I2C 2
000370H 000374H to 00038CH 000390H 000394H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH
Reserved
Reserved ROMS [R] 11111111 00000000 Reserved BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Reserved
ROM Select Register
Reserved
Bit Search Module
(Continued) 35
MB91460R Series
Address 000400H to 00043CH 000440H
Register +0 +1 Reserved ICR00 [R/W] B, H, W ---11111 ICR04 [R/W] B, H, W ---11111 ICR08 [R/W] B, H, W ---11111 ICR12 [R/W] B, H, W ---11111 ICR16 [R/W] B, H, W ---11111 ICR20 [R/W] B, H, W ---11111 Reserved ICR01 [R/W] B, H, W ---11111 ICR05 [R/W] B, H, W ---11111 ICR09 [R/W] B, H, W ---11111 ICR13 [R/W] B, H, W ---11111 Reserved ICR21 [R/W] B, H, W ---11111 ICR25 [R/W] B, H, W ---11111 ICR29 [R/W] B, H, W ---11111 Reserved Reserved ICR38 [R/W] B, H, W ---11111 ICR42 [R/W] B, H, W ---11111 Reserved ICR48 [R/W] B, H, W ---11111 ICR49 [R/W] B, H, W ---11111 ICR50 [R/W] B, H, W ---11111 ICR58 [R/W] B, H, W ---11111 ICR51 [R/W] B, H, W ---11111 ICR59 [R/W] B, H, W ---11111 ICR39 [R/W] B, H, W ---11111 ICR43 [R/W] B, H, W ---11111 ICR22 [R/W] B, H, W ---11111 ICR26 [R/W] B, H, W ---11111 ICR02 [R/W] B, H, W ---11111 ICR06 [R/W] B, H, W ---11111 Reserved ICR03 [R/W] B, H, W ---11111 ICR07 [R/W] B, H, W ---11111 ICR11 [R/W] B, H, W ---11111 +2 +3
Block
Reserved
000444H
000448H
Interrupt Control Unit
00044CH
Reserved ICR19 [R/W] B, H, W ---11111 ICR23 [R/W] B, H, W ---11111 ICR27 [R/W] B, H, W ---11111
000450H
000454H
000458H
00045CH 000460H 000464H
Reserved
Reserved
Interrupt Control
000468H 00046CH 000470H 000474H 000478H
Reserved
Reserved Reserved
(Continued) 36
MB91460R Series
Address
Register +0 Reserved RSRR [R/W] B, H, W 10000000 CLKR [R/W] B, H, W ---- 0000 +1 ICR61 [R/W] B, H, W ---11111 STCR [R/W] B, H, W 00110011 WPR [W] B, H, W XXXXXXXX +2 ICR62 [R/W] B, H, W ---11111 TBCR [R/W] B, H, W 00XXX - 00 DIVR0 [R/W] B, H, W 00000011 +3 ICR63 [R/W] B, H, W ---11111 CTBR [W] B, H, W XXXXXXXX DIVR1 [R/W] B, H, W 00000000 PLLDIVG [W] B, H 00000000
Block Interrupt Control
00047CH
000480H
Clock Control
000484H 000488H 00048CH
Reserved PLLDIVM [R/W] PLLDIVN [R/W] PLLDIVG [R/W] B, H B, H B, H - - - 00000 - - - 00000 - - - 00000 PLLCTRL [R/W] B, H - - - - 0000 Reserved
Reserved
PLL Interface
000490H 000494H to 00049CH 0004A0H
Reserved WTCER [R/W] B, H - - - - - - 00
Reserved
Reserved
WTCR [R/W] B, H 00000000 000 - 00 - 0 Real Time Clock
0004A4H
Reserved WTHR [R/W] B, H - - - 00000
WTBR [R/W] B, B, H - - - XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] B, H - - 000000 WTSR [R/W] B - - 000000 CSCFG [R/W] 0X000000 Reserved CMCFG [R/W] 00000000
0004A8H
0004ACH 0004B0H 0004B4H 0004B8H 0004BCH
Reserved CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTR1 [R] - - - - - - - - 00000000 CMPR [R/W] - - 000010 11111101 CMT1 [R/W] 00000000 1 - - - 0000 CANPRE [R/W] B, H 0 - - - 0000 LVSEL [R/W] 00000111 LVDET [R/W] 0000 0 - 00
Clock Monitor
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000 Reserved CMCR [R/W] - 001 - - 00
Calibration of Sub Clock
CMT2 [R/W] - - 000000 - - 000000 Reserved
Clock Modulation
0004C0H
CAN (Clock Control)
0004C4H
Reserved
Low Voltage Detection (Continued) 37
MB91460R Series
Address 0004C8H 0004CCH 0004D4H 0004D8H 0004DCH to 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H to 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH
Register +0 OSCRH [R/W] 000 - - 001 OSCCR [R/W] -------0 SHDE [R/W] B 0------Reserved +1 OSCRL [R/W] - - - - - 000 +2 WPCRH [R/W] 00 - - - 000 Reserved EXTE [R/W] B, H EXTF [R/W] B, H 00000000 00000000 Reserved +3 WPCRL [R/W] - - - - - - 00
Block Main-/Sub-Oscillation Stabilization Wait Timer Main- Oscillation Standby Control
EXTLV [R/W] B, H 00000000 00000000 Reserved ASR0 [R/W] B, H, W 00000000 00000000 ASR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ASR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ASR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ASR4 [R/W] B, H, W XXXXXXXX XXXXXXXX Reserved AWR0 [R/W] B, H, W 01001111 11111011 AWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR4 [R/W] B, H, W XXXXXXXX XXXXXXXX Reserved MCRA [R/W] B, H, W XXXXXXXX IORW0 [R/W] B, H, W XXXXXXXX MCRB [R/W] B, H, W XXXXXXXX Reserved IORW1 [R/W] B, H, W XXXXXXXX
Shutdown control
Reserved ACR0 [R/W] B, H, W 1111**00 00100000 ACR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR4 [R/W] B, H, W XXXXXXXX XXXXXXXX External Bus Unit
AWR1 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR3 [R/W] B, H, W XXXXXXXX XXXXXXXX Reserved Reserved Reserved External Bus Unit Reserved
IORW2 [R/W] B, H, W XXXXXXXX
Reserved (Continued)
38
MB91460R Series
Address
Register +0 CSER [R/W] B, H, W 00000001 RCRH [R/W] B, H, W 00XXXXXX +1 CHER [R/W] B, H, W 11111111 RCRL [R/W] B, H, W XXXX0XXX Reserved MODR [W] B XXXXXXXX Reserved IOS [R/W] 00000000 +2 Reserved +3 TCR [R/W] B, H, W 00000000
Block
000680H
External Bus Unit
000684H 000688H to 0007F8H 0007FCH 000800H to 000BFCH 000C00H 000C04H to 000CFCH 000D00H 000D04H 000D08H 000D0CH 000D10H 000D14H 000D18H 000D1CH 000D20H to 000D3CH
Reserved
Reserved
Reserved
Reserved
Mode Register
Reserved
Reserved
I-Unit
Reserved PDRD00 [R] B, H PDRD01 [R] B, H XXXXXXXX XXXXXXXX Reserved
Reserved
Reserved
PDRD05 [R] B, H PDRD06 [R] B, H PDRD07 [R] B, H XXXXXXXX XXXXXXXX XXXXXXXX
PDRD08 [R] B, H PDRD09 [R] B, H PDRD10 [R] B, H PDRD11 [R] B, H XXXX - - XX - - - XXXXX - XXXXXXX - - - - - - XX Reserved PDRD13 [R] B, H PDRD14 [R] B, H PDRD15 [R] B, H - - - - - XXX - - - - XXXX - - - - XXXX Port Data Direct Read Register
PDRD16 [R] B, H PDRD17 [R] B, H PDRD18 [R] B, H PDRD19 [R] B, H X------XXXXXXXX - - - - - XXX - XXX - XXX PDRD20 [R] B, H PDRD21 [R] B, H PDRD22 [R] B, H PDRD23 [R] B, H - XXX - XXX - XXX - XXX XXXXXX - X - X - XXXXX PDRD24 [R] B, H XXXXXXXX PDRD28 [R] B, H PDRD29 [R] B, H XXXXXXXX XXXXXXXX Reserved Reserved Reserved
Reserved (Continued)
39
MB91460R Series
Address
Register +0 DDR00 [R/W] B, H 00000000 Reserved DDR08 [R/W] B, H 0000 - - 00 Reserved DDR16 [R/W] B, H 0------DDR20 [R/W] B, H - 000 - 000 DDR24 [R/W] B, H 00000000 DDR28 [R/W] B, H 00000000 DDR29 [R/W] B, H 00000000 Reserved +1 DDR01 [R/W] B, H 00000000 DDR05 [R/W] B, H 00000000 DDR09 [R/W] B, H - - - 00000 DDR13 [R/W] B, H - - - - - 000 DDR17 [R/W] B, H 00000000 DDR21 [R/W] B, H - 000 - 000 +2 Reserved DDR06 [R/W] B, H 00000000 DDR10 [R/W] B, H - 0000000 DDR14 [R/W] B, H - - - - 0000 DDR18 [R/W] B, H - - - - - 000 DDR22 [R/W] B, H 000000 - 0 Reserved DDR07 [R/W] B, H 00000000 DDR11 [R/W] B, H - - - - - - 00 DDR15 [R/W] B, H - - - - 0000 DDR19 [R/W] B, H - 000 - 000 DDR23 [R/W] B, H - 0 - 00000 +3
Block
000D40H
000D44H
000D48H
000D4CH
Port Direction Register
000D50H
000D54H
000D58H
000D5CH 000D60H to 000D7CH
Reserved
Reserved (Continued)
40
MB91460R Series
Address
Register +0 PFR00 [R/W] B, H 11111111 Reserved PFR08 [R/W] B, H 1111 - - 11 Reserved PFR16 [R/W] B, H 0------PFR20 [R/W] B, H - 000 - 000 PFR24 [R/W] B, H 00000000 PFR28 [R/W] B, H 00000000 PFR29 [R/W] B, H 00000000 Reserved EPFR10 [R/W] B, H - - 00 - - - 0 EPFR14 [R/W] B, H - - - - 0000 EPFR18 [R/W] B, H -----0-+1 PFR01 [R/W] B, H 11111111 PFR05 [R/W] B, H 11111111 PFR09 [R/W] B, H - - - 11111 PFR13 [R/W] B, H - - - - - 000 PFR17 [R/W] B, H 00000000 PFR21 [R/W] B, H - 000 - 000 +2 Reserved PFR06 [R/W] B, H 11111111 PFR10 [R/W] B, H - 1111111 PFR14 [R/W] B, H - - - - 0000 PFR18 [R/W] B, H - - - - - 000 PFR22 [R/W] B, H 000000 - 0 Reserved PFR07 [R/W] B, H 11111111 PFR11 [R/W] B, H - - - - - - 00 PFR15 [R/W] B, H - - - - 0000 PFR19 [R/W] B, H - 000 - 000 PFR23 [R/W] B, H - 0 - 00000 +3
Block
000D80H
000D84H
000D88H
000D8CH
Port Function Register
000D90H
000D94H
000D98H
000D9CH 000DA0H to 000DC4H 000DC8H
Reserved
Reserved
Reserved EPFR13 [R/W] B, H -----0-Reserved EPFR21 [R/W] B, H -0---0--
Reserved EPFR15 [R/W] B, H - - - - 0000 EPFR19 [R/W] B, H -0---0-Extended Port Function Register
000DCCH
Reserved EPFR16 [R/W] B, H 0------EPFR20 [R/W] B, H -0---0--
000DD0H
000DD4H 000DD8H, 000DDCH
Reserved
Reserved (Continued)
41
MB91460R Series
Address 000DE0H to 000DFCH 000E00H
Register +0 +1 Reserved PODR00 [R/W] B, H 00000000 Reserved PODR08 [R/W] B, H 0000 - - 00 Reserved PODR16 [R/W] B, H 0------PODR20 [R/W] B, H - 000 - 000 PODR24 [R/W] B, H 00000000 PODR28 [R/W] B, H 00000000 PODR29 [R/W] B, H 00000000 Reserved PODR01 [R/W] B, H 00000000 PODR05 [R/W] B, H 00000000 PODR09 [R/W] B, H - - - 00000 PODR13 [R/W] B, H - - - - - 000 PODR17 [R/W] B, H 00000000 PODR21 [R/W] B, H - 000 - 000 +2 +3
Block
Reserved
Reserved PODR06 [R/W] B, H 00000000 PODR10 [R/W] B, H - 0000000 PODR14 [R/W] B, H - - - - 0000 PODR18 [R/W] B, H - - - - - 000 PODR22 [R/W] B, H 000000 - 0 Reserved PODR07 [R/W] B, H 00000000 PODR11 [R/W] B, H - - - - - - 00 PODR15 [R/W] B, H - - - - 0000 PODR19 [R/W] B, H - 000 - 000 PODR23 [R/W] B, H - 0 - 00000
000E04H
000E08H
000E0CH
Port Output Select Register
000E10H
000E14H
000E18H
000E1CH 000E20H to 000E3CH
Reserved
Reserved (Continued)
42
MB91460R Series
Address
Register +0 PILR00 [R/W] B, H 00000000 Reserved PILR08 [R/W] B, H 0000 - - 00 Reserved PILR16 [R/W] B, H 0------PILR20 [R/W] B, H - 000 - 000 PILR24 [R/W] B, H 00000000 PILR28 [R/W] B, H 00000000 PILR29 [R/W] B, H 00000000 Reserved +1 PILR01 [R/W] B, H 00000000 PILR05 [R/W] B, H 00000000 PILR09 [R/W] B, H - - - 00000 PILR13 [R/W] B, H - - - - - 000 PILR17 [R/W] B, H 00000000 PILR21 [R/W] B, H - 000 - 000 +2 Reserved PILR06 [R/W] B, H 00000000 PILR10 [R/W] B, H - 0000000 PILR14 [R/W] B, H - - - - 0000 PILR18 [R/W] B, H - - - - - 000 PILR22 [R/W] B, H 000000 - 0 Reserved PILR07 [R/W] B, H 00000000 PILR11 [R/W] B, H - - - - - - 00 PILR15 [R/W] B, H - - - - 0000 PILR19 [R/W] B, H - 000 - 000 PILR23 [R/W] B, H - 0 - 00000 +3
Block
000E40H
000E44H
000E48H
000E4CH
Input Level Select Register
000E50H
000E54H
000E58H
000E5CH 000E60H to 000E7CH 000E80H to 000E88H 000E8CH
Reserved
Reserved
Reserved EPILR14 [R/W] B, H - - - - 0000 EPILR18 [R/W] B, H 000000 - 0 EPILR22 [R/W] B, H 000000 - 0 Reserved (Continued) EPILR15 [R/W] B, H - - - - 0000 EPILR19 [R/W] B, H - 000 - 000 EPILR23 [R/W] B, H - 0 - 00000 Port Input Level Select Register
Reserved EPILR17 [R/W] B, H - - - - 0000 EPILR21 [R/W] B, H - 000 - 000
000E90H
Reserved EPILR20 [R/W] B, H - 000 - 000 EPILR24 [R/W] B, H 00 - - 0000
000E94H
000E98H
43
MB91460R Series
Address 000E9CH to 000EBCH 000EC0H
Register +0 +1 Reserved PPER00 [R/W] B, H 00000000 Reserved PPER08 [R/W] B, H 0000 - - 00 Reserved PPER16 [R/W] B, H 0------PPER20 [R/W] B, H - 000 - 000 PPER24 [R/W] B, H 00 - - 0000 PPER28 [R/W] B, H 00000000 PPER29 [R/W] B, H 00000000 Reserved PPCR00 [R/W] B, H 11111111 Reserved PPCR08 [R/W] B, H 1111 - -11 PPCR01 [R/W] B, H 11111111 PPCR05 [R/W] B, H 11111111 PPCR09 [R/W] B, H - - - 11111 PPER01 [R/W] B, H 00000000 PPER05 [R/W] B, H 00000000 PPER09 [R/W] B, H - - - 00000 PPER13 [R/W] B, H - - - - - 000 PPER17 [R/W] B, H 00000000 PPER21 [R/W] B, H - 000 - 000 +2 +3
Block
Reserved
Reserved PPER06 [R/W] B, H 00000000 PPER10 [R/W] B, H - 0000000 PPER14 [R/W] B, H - - - - 0000 PPER18 [R/W] B, H - - - - - 000 PPER22 [R/W] B, H - - - - 00 - 0 Reserved PPER07 [R/W] B, H 00000000 PPER11 [R/W] B, H - - - - - - 00 PPER15 [R/W] B, H - - - - 0000 PPER19 [R/W] B, H - 000 - 000 PPER23 [R/W] B, H - 0 - 00000
000EC4H
000EC8H
000ECCH
Port Pull-Up/Pull-Down Enable Register
000ED0H
000ED4H
000ED8H
000EDCH 000EE0H to 000EFCH 000F00H
Reserved
Reserved
Reserved PPCR06 [R/W] B, H 11111111 PPCR10 [R/W] B, H - 1111111 PPCR07 [R/W] B, H 11111111 PPCR11 [R/W] B, H - - - - - -11 (Continued)
000F04H
Port Pull-Up/Pull-Down Control Register
000F08H
44
MB91460R Series
Address
Register +0 Reserved PPCR16 [R/W] B, H 1------PPCR20 [R/W] B, H - 111 - 111 PPCR24 [R/W] B, H 11 - - 1111 PPCR28 [R/W] B, H 11111111 PPCR29 [R/W] B, H 11111111 Reserved DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved +1 PPCR13 [R/W] B, H - - - - - 111 PPCR17 [R/W] B, H 11111111 PPCR21 [R/W] B, H - 111 - 111 +2 PPCR14 [R/W] B, H - - - - 1111 PPCR18 [R/W] B, H - - - - - 111 PPCR22 [R/W] B, H 111111 - 1 Reserved +3 PPCR15 [R/W] B, H - - - - 1111 PPCR19 [R/W] B, H - 111 - 111 PPCR23 [R/W] B, H - 1 - 11111
Block
000F0CH
000F10H
000F14H
Port Pull-Up/Pull-Down Control Register
000F18H
000F1CH 000F20H to 000F3CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 005FFCH
Reserved
Reserved
DMAC
Reserved (Continued) 45
MB91460R Series
Address 006000H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 00BFFCH 00C000H 00C004H 00C008H 00C00CH 00C010H 00C014H 00C018H 00C01CH 00C020H 00C024H 00C028H, 00C02CH 00C030H
Register +0 +1 Reserved FMCS [R/W] 01101000 FMCR [R] - - - 00000 FCHCR [R/W] - - - - - - 00 10000011 FMWT2 [R] - 001 - - - FMPS [R/W] - - - - - 000 +2 +3
Block
Reserved
FMWT [R/W] 11111111 11111111
Flash Memory/ Cache Control Register
FMAC [R] 00000000 00000000 00000000 00000000 FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000 FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000 Reserved CTRLR0 [R/W] B, H 00000000 00000001 ERRCNT0 [R] B, H, W 00000000 00000000 INTR0 [R] B, H, W 00000000 00000000 BRPE0 [R/W] B, H, W 00000000 00000000 IF1CREQ0 [R/W] B, H 00000000 00000001 IF1MSK20 [R/W] B, H, W 11111111 11111111 IF1ARB20 [R/W] B, H, W 00000000 00000000 IF1MCTR0 [R/W] B, H, W 00000000 00000000 IF1DTA10 [R/W] B, H, W 00000000 00000000 IF1DTB10 [R/W] B, H 00000000 00000000 Reserved IF1DTA20 [R/W] B, H, W 00000000 00000000 IF1DTA10 [R/W] B, H, W 00000000 00000000 (Continued) STATR0 [R/W] B, H 00000000 00000000 BTR0 [R/W] B, H, W 00100011 00000001 TESTR0 [R/W] B, H, W 00000000 X0000000 Reserved IF1CMSK0 [R/W] B, H 00000000 00000000 IF1MSK10 [R/W] B, H, W 11111111 11111111 IF1ARB10 [R/W] B, H, W 00000000 00000000 Reserved IF1DTA20 [R/W] B, H, W 00000000 00000000 IF1DTB20 [R/W] B, H 00000000 00000000 CAN 0 IF 1 Register CAN 0 Control Register I-Cache Non-cacheable area setting Register Reserved
46
MB91460R Series
Address 00C034H 00C038H, 00C03CH 00C040H 00C044H 00C048H 00C04CH 00C050H 00C054H 00C058H, 00C05CH 00C060H 00C064H 00C068H to 00C07CH 00C080H 00C084H to 00C08CH 00C090H 00C094H to 00C09CH 00C0A0H
Register +0 +1 +2 +3 IF1DTB20 [R/W] B, H, W 00000000 00000000 Reserved IF2CREQ0 [R/W] B, H 00000000 00000001 IF2MSK20 [R/W] B, H, W 11111111 11111111 IF2ARB20 [R/W] B, H, W 00000000 00000000 IF2MCTR0 [R/W] B, H, W 00000000 00000000 IF2DTA10 [R/W] B, H, W 00000000 00000000 IF2DTB10 [R/W] B, H, W 00000000 00000000 Reserved IF2DTA20 [R/W] B, H, W 00000000 00000000 IF2DTB20 [R/W] B, H, W 00000000 00000000 Reserved TREQR20 [R] B, H, W 00000000 00000000 Reserved NEWDT20 [R] B, H, W 00000000 00000000 Reserved INTPND20 [R] B, H, W 00000000 00000000 INTPND10 [R] B, H, W 00000000 00000000 NEWDT10 [R] B, H, W 00000000 00000000 TREQR10 [R] B, H, W 00000000 00000000 IF2DTA10 [R/W] B, H, W 00000000 00000000 IF2DTB10 [R/W] B, H, W 00000000 00000000 IF2CMSK0 [R/W] B, H 00000000 00000000 IF2MSK10 [R/W] B, H, W 11111111 11111111 IF2ARB10 [R/W] B, H, W 00000000 00000000 Reserved IF2DTA20 [R/W] B, H, W 00000000 00000000 IF2DTB20 [R/W] B, H, W 00000000 00000000 IF1DTB10 [R/W] B, H, W 00000000 00000000
Block
CAN 0 IF 1 Register
CAN 0 IF 2 Register
CAN 0 Status Flags
(Continued)
47
MB91460R Series
Address 00C0A4H to 00C0ACH 00C0B0H 00C0B4H to 00C0FCH 00C100H 00C104H 00C108H 00C10CH 00C110H 00C114H 00C118H 00C11CH 00C120H 00C124H 00C128H, 00C12CH 00C130H 00C134H 00C138H, 00C13CH
Register +0 +1 Reserved MSGVAL20 [R] B, H, W 00000000 00000000 Reserved CTRLR1 [R/W] B, H 00000000 00000001 ERRCNT1 [R] B, H, W 00000000 00000000 INTR1 [R] B, H, W 00000000 00000000 BRPE1 [R/W] B, H, W 00000000 00000000 IF1CREQ1 [R/W] B, H 00000000 00000001 IF1MSK21 [R/W] B, H, W 11111111 11111111 IF1ARB21 [R/W] B, H, W 00000000 00000000 IF1MCTR1 [R/W] B, H, W 00000000 00000000 IF1DTA11 [R/W] B, H, W 00000000 00000000 IF1DTB11 [R/W] B, H, W 00000000 00000000 Reserved IF1DTA21 [R/W] B, H, W 00000000 00000000 IF1DTB21 [R/W] B, H, W 00000000 00000000 Reserved IF1DTA11 [R/W] B, H, W 00000000 00000000 IF1DTB11 [R/W] B, H, W 00000000 00000000 STATR1 [R/W] B, H 00000000 00000000 BTR1 [R/W] B, H, W 00100011 00000001 TESTR1 [R/W] B, H, W 00000000 X0000000 Reserved IF1CMSK1 [R/W] B, H 00000000 00000000 IF1MSK11 [R/W] B, H, W 11111111 11111111 IF1ARB11 [R/W] B, H, W 00000000 00000000 Reserved IF1DTA21 [R/W] B, H, W 00000000 00000000 IF1DTB21 [R/W] B, H, W 00000000 00000000 MSGVAL10 [R] B, H, W 00000000 00000000 +2 +3
Block
CAN 0 Status Flags
Reserved
CAN 1 Control Register
CAN 1 IF 1 Register
(Continued)
48
MB91460R Series
Address 00C140H 00C144H 00C148H 00C14CH 00C150H 00C154H 00C158H, 00C15CH 00C160H 00C164H 00C168H to 00C17CH 00C180H 00C184H 00C188H, 00C18CH 00C190H 00C194H 00C198H, 00C19CH 00C1A0H 00C1A4H
Register +0 +1 +2 +3 IF2CREQ1 [R/W] B, H 00000000 00000001 IF2MSK21 [R/W] B, H, W 11111111 11111111 IF2ARB21 [R/W] B, H, W 00000000 00000000 IF2MCTR1 [R/W] B, H, W 00000000 00000000 IF2DTA11 [R/W] B, H, W 00000000 00000000 IF2DTB11 [R/W] B, H, W 00000000 00000000 Reserved IF2DTA21 [R/W] B, H, W 00000000 00000000 IF2DTB21 [R/W] B, H, W 00000000 00000000 Reserved TREQR21 [R] B, H, W 00000000 00000000 TREQR41 [R] B, H, W 00000000 00000000 Reserved NEWDT21 [R] B, H, W 00000000 00000000 NEWDT41 [R] B, H, W 00000000 00000000 Reserved INTPND21 [R] B, H, W 00000000 00000000 INTPND41 [R] B, H, W 00000000 00000000 INTPND11 [R] B, H, W 00000000 00000000 INTPND31 [R] B, H, W 00000000 00000000 NEWDT11 [R] B, H, W 00000000 00000000 NEWDT31 [R] B, H, W 00000000 00000000 TREQR11 [R] B, H, W 00000000 00000000 TREQR31 [R] B, H, W 00000000 00000000 IF2DTA11 [R/W] B, H, W 00000000 00000000 IF2DTB11 [R/W] B, H, W 00000000 00000000 IF2CMSK1 [R/W] B, H 00000000 00000000 IF2MSK11 [R/W] B, H, W 11111111 11111111 IF2ARB11 [R/W] B, H, W 00000000 00000000 Reserved IF2DTA21 [R/W] B, H, W 00000000 00000000 IF2DTB21 [R/W] B, H, W 00000000 00000000
Block
CAN 1 IF 2 Register
CAN 1 Status Flags
(Continued)
49
MB91460R Series
Address 00C1A8H, 00C1ACH 00C1B0H 00C1B4H 00C1B8H to 00EFFCH 00F000H 00F004H 00F008H 00F00CH 00F010H 00F014H to 00F01CH 00F020H 00F024H 00F028H 00F02CH 00F030H to 00F07CH 00F080H 00F084H 00F088H
Register +0 +1 Reserved MSGVAL21 [R] B, H, W 00000000 00000000 MSGVAL41 [R] B, H, W 00000000 00000000 Reserved BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 MSGVAL11 [R] B, H, W 00000000 00000000 MSGVAL31 [R] B, H, W 00000000 00000000 +2 +3
Block
CAN 1 Status Flags
EDSU / MPU Reserved BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 Reserved BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) EDSU / MPU Reserved
50
MB91460R Series
Address 00F08CH 00F090H 00F094H 00F098H 00F09CH 00F0A0H 00F0A4H 00F0A8H 00F0ACH 00F0B0H 00F0B4H 00F0B8H 00F0BCH 00F0C0H to 027FFCH 024000H to 02BFFCH 02C000H to 02FFFCH 030000H to 033FFCH 034000H to 03FFFCH
Register +0 +1 +2 +3 BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved
Block
EDSU / MPU
Reserved
D-RAM 32 Kbytes : 024000H to 02BFFCH (data : 1 wait) D-RAM 16 Kbytes : 02C000H to 02FFFCH (data : 0 wait) I-/D-RAM size is 16 Kbytes : 030000H to 033FFCH (instruction : 0 wait, data : 1 wait)
D-RAM 32 Kbytes D-RAM 16 Kbytes I-/D-RAM 16 Kbytes
Reserved
Reserved (Continued) 51
MB91460R Series
(Continued) Address 040000H to 05FFFCH 060000H to 07FFFCH 080000H to 09FFFCH 0A0000H to 0BFFFCH 0C0000H to 0DFFFCH 0E0000H to 0FFFF4H 0FFFF8H 0FFFFCH 100000H to 13FFFCH 140000H to 17FFFCH 180000H to 4FFFFCH Register +0 +1 +2 +3 Block
ROMS00 area (128 Kbytes)
ROMS01 area (128 Kbytes)
ROMS02 area (128 Kbytes) Memory area ROMS03 area (128 Kbytes)
ROMS04 area (128 Kbytes)
ROMS05 area (128 Kbytes) Mode Vector Reset Vector ROMS06 area (256 Kbytes) Memory area ROMS07 area (256 Kbytes)
Reset/Mode Vector
Reserved
Reserved
* : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
52
MB91460R Series
INTERRUPT VECTOR TABLE
Interrupt number Interrupt Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) Memory Protection exception System reserved System reserved INTE instruction System reserved System reserved System reserved System reserved Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B Interrupt level Setting Register Register address Interrupt vector*1 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H Default Vector address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H (Continued) 0 1 2 3 RN
15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 440H 441H 442H 443H 444H 445H
53
MB91460R Series
Interrupt number Interrupt External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 System reserved System reserved System reserved Reload Timer 7 Free Run Timer 0 Free Run Timer 1 Free Run Timer 2 Free Run Timer 3 System reserved System reserved System reserved System reserved CAN 0 CAN 1 System reserved System reserved System reserved System reserved LIN-USART 0 RX LIN-USART 0 TX LIN-USART 1 RX LIN-USART 1 TX LIN-USART 2 RX LIN-USART 2 TX LIN-USART 3 RX LIN-USART 3 TX Decimal 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Hexadecimal 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D
Interrupt level Setting Register ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 Register address 446H 447H 448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H 456H
Interrupt vector*1 Offset 38CH 388H 384H 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H Default Vector address 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H (Continued) 6 7 8 9 4 5 RN
54
MB91460R Series
Interrupt number Interrupt System reserved Delayed Interrupt System reserved*2 System reserved*
2
Interrupt level Setting Register ICR23*3 (ICR24) ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 Register address 457H (458H) 459H 45AH 45BH 45CH 45DH 45EH 45FH 460H 461H 462H 463H 464H 465H 466H 467H
Interrupt vector*1 Offset 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H 28CH 288H 284H 280H Default Vector address 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFEB8H 000FFEB4H 000FFEB0H 000FFEACH 000FFEA8H 000FFEA4H 000FFEA0H 000FFE9CH 000FFE98H 000FFE94H 000FFE90H 000FFE8CH 000FFE88H 000FFE84H 000FFE80H (Continued) 55 10 11 12 13 RN
Decimal 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
Hexadecimal 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
LIN-USART4 (FIFO) RX LIN-USART4 (FIFO) TX LIN-USART5 (FIFO) RX LIN-USART5 (FIFO) TX LIN-USART6 (FIFO) RX LIN-USART6 (FIFO) TX System reserved System reserved IC0/IC2 I2C 1 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3
2 2
MB91460R Series
Interrupt number Interrupt System reserved System reserved System reserved System reserved Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Prog. Pulse Gen. 0 Prog. Pulse Gen. 1 Prog. Pulse Gen. 2 Prog. Pulse Gen. 3 Prog. Pulse Gen. 4 Prog. Pulse Gen. 5 Prog. Pulse Gen. 6 Prog. Pulse Gen. 7 System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Decimal 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Hexadecimal 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81
Interrupt level Setting Register ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47*3 ICR48 ICR49 ICR50 ICR51 ICR52 ICR53 ICR54 ICR55 ICR56 Register address 468H 469H 46AH 46BH 46CH 46DH 46EH 46FH 470H 471H 472H 473H 474H 475H 476H 477H 478H
Interrupt vector*1 Offset 27CH 278H 274H 270H 26CH 268H 264H 260H 25CH 258H 254H 250H 24CH 248H 244H 240H 23CH 238H 234H 230H 22CH 228H 224H 220H 21CH 218H 214H 210H 20CH 208H 204H 200H 1FCH 1F8H Default Vector address 000FFE7CH 000FFE78H 000FFE74H 000FFE70H 000FFE6CH 000FFE68H 000FFE64H 000FFE60H 000FFE5CH 000FFE58H 000FFE54H 000FFE50H 000FFE4CH 000FFE48H 000FFE44H 000FFE40H 000FFE3CH 000FFE38H 000FFE34H 000FFE30H 000FFE2CH 000FFE28H 000FFE24H 000FFE20H 000FFE1CH 000FFE18H 000FFE14H 000FFE10H 000FFE0CH 000FFE08H 000FFE04H 000FFE00H 000FFDFCH 000FFDF8H (Continued) 15 RN
56
MB91460R Series
(Continued) Interrupt number Interrupt System reserved System reserved Real Time Clock Calibration Unit A/D Converter 0 System reserved System reserved System reserved Low Voltage Detection System reserved Timebase Overflow PLL Clock Gear DMA Controller Main/Sub OSC stability wait System reserved Used by the INT instruction. Decimal 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 to 255 Hexadecimal 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 to FF Interrupt level Setting Register ICR57 ICR58 ICR59 ICR60 ICR61 ICR62 ICR63 Register address 479H 47AH 47BH 47CH 47DH 47EH 47FH Interrupt vector*1 Offset 1F4H 1F0H 1ECH 1E8H 1E4H 1E0H 1DCH 1D8H 1D4H 1D0H 1CCH 1C8H 1C4H 1C0H 1BCH 1B8H to 000H Default Vector address 000FFDF4H 000FFDF0H 000FFDECH 000FFDE8H 000FFDE4H 000FFDE0H 000FFDDCH 000FFDD8H 000FFDD4H 000FFDD0H 000FFDCCH 000FFDC8H 000FFDC4H 000FFDC0H 000FFDBC 000FFDB8H to 000FFC00H 14 RN
*1 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top address of the EIT vector table. The default vector address are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. *2 : Used by REALOS *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03 : IOS[0])
57
MB91460R Series
ELECTRICAL CHARACTERISTICS
1. Absolute maximum rating
Parameter Power supply voltage 1*1 Power supply voltage 2*1 Analog power supply voltage* Input voltage 1*1 Input voltage 2*1 Analog pin input voltage* Output voltage 1*
1 1 1 1
Symbol VCC3 VCC5 AVCC3 AVRH VI1 VI2 VIA VO1 VO2 ICLAMP |ICLAMP| IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Rating Min Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 Vss - 0.3 - 2.0 - 40 - 55 Max Vss + 4.0 Vss + 6.0 Vss + 4.0 Vss + 4.0 Vcc3 + 0.3 Vcc5 + 0.3 AVcc3 + 0.3 Vcc3 + 0.3 Vcc5 + 0.3 + 2.0 20 10 8 100 50 - 10 -4 - 50 - 20 1000 + 85 + 125
Unit V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C
Remarks
*2 *2
Analog power supply voltage*
Output voltage 2*1 Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operation ambient temperature Storage temperature
*3 *3 *4 *5 *6 *6 *5 *6
*1 : The parameter is based on VSS = AVSS = 0.0 V. *2 : Be careful not to exceed "VCC + 0.3 V", for example, when the power is turned on. Also, do not let AVCC3 exceed VCC3. *3 : * * * * Relevant pins : Pins that are used as I/O ports or that are shared as I/O ports Use within recommended operating conditions. Use at DC voltage (current). The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that, when the microcontroller drive current is low as in low power consumption mode, the +B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. * Note that, if the +B signal is input exists when the microcontroller is off (not fixed at 0 V) , power is supplied through the pin, possibly causing the microcontroller to operate imperfectly. (Continued)
58
MB91460R Series
(Continued) * Note that, if the +B input exists when the power supply is turned on, power is supplied through the pin, possibly resulting in a power-supply voltage at which a power-on reset does not work. * Be careful not to let the +B input pin open. * Example of recommended circuit : * Input/output equivalent circuit
Protective diode
VCC
Limiting resistor +B input (0 V to 16 V)
P-ch
N-ch
R
*4 : The maximum output current is the peak value for a single pin. *5 : The average output current is the average current for a single pin over a period of 100 ms. *6 : The total average output current is the average current for all pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
59
MB91460R Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC5 Power supply voltage VCC3 AVCC3 Value Min 4.5 3.0 3.0 Typ Max 5.5 3.6 3.6 Unit V V V Use a ceramic capacitor or a capacitor having the similar frequency characteristic. For a smoothing capacitor of VCC5 pin (VCC3 pin) , use one having a capacitance value greater than CS. Remarks
Smoothing capacitor
CS
4.7 (accuracy within 50%)
F
Operating temperature
TA
- 40
+ 85
C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
C_1
C_2
VSS CS
AVSS CS
60
MB91460R Series
3. DC characteristics
(VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Pin name CMOS hysteresis input CMOS hysteresis input CMOS input Automotive input I2C input CMOS hysteresis input CMOS hysteresis input CMOS input Automotive input I2C input 3.3 V, 5 V switch pin 3.3 V dedicated pin 3.3 V, 5 V switch pin 3.3 V dedicated pin I2C pin Input pin Condition Value Min 0.8 x VCC Typ Max VCC + 0.3 Unit Remarks
VIH1
V
*2
"H" level input voltage
VIH2 VIH3 VIH4 VIH5 VIL1

0.7 x VCC 0.7 x VCC 0.8 x VCC 0.7 x VCC3 VSS - 0.3

VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC5 + 0.3 0.2 x VCC
V V V V V *2 *1
"L" level
VIL2 VIL3 VIL4 VIL5
VCC = 5.0 V, IOH = 5.0 mA/ VCC = 3.3 V, IOH = 2.0 mA VCC3 = 3.3 V, IOH = 4.0 mA VCC = 5.0 V, IOL = 5.0 mA/ VCC = 3.3 V, IOL = 2.0 mA VCC3 = 3.3 V, IOL = 4.0 mA VCC3 = 3.3 V, IOL = 3.0 mA VCC = AVCC = 5.0 V, VSS < VI < VCC
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5

0.3 x VCC 0.3 x VCC 0.5 x VCC 0.3 x VCC3
V V V V *1
input voltage
"H" level
VOH1
V
output voltage VOH2
VCC3 - 0.5
V
VOL1
"L" level
0.4
V
output voltage
VOL2 VOL3
-5 25
50
0.4 0.4 +5 100
V V A k (Continued) 61
Input leak current Pull-up resistance value
IIL
RUP
INIT, pull-up pin
MB91460R Series
(Continued) (VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Symbol Pin name INIT, pull-up pin Condition Value Min 25 Typ 50 Max 100 Unit Remarks
Parameter Pull-down resistance value
RDOWN
CPU core : 80 MHz, External bus : 40 MHz (no-load) , Peripheral macro : 10 MHz, CAN : 20 MHz + 85 C + 85 C
k
ICC3 Power supply current ICC5 ICCH ICCH Input capacitance
VCC3
120
150
mA
VCC5 VCC3 VCC3 Except VCC, VSS, AVCC3, AVSS, AVRH

15 1 10
20 3 50
mA mA A pF At stop At shutdown
CIN
5
15
*1 : Only 3.3 V pins and MD0 pin, MD1 pin and MD2 pin as I/O power supply *2 : Including the INIT pin, MD3 pin, and NMI pin.
62
MB91460R Series
4. AC characteristics
(1) Clock timing (VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40 C to + 85 C) Parameter Clock frequency Clock cycle time Clock frequency Clock cycle time Symbol fC tC fCS tCS fCP Internal operation clock frequency fCPP fCPT fCAN tCP Internal operation clock cycle time tCPP tCPT tCAN Pin name X0 X1 X0 X1 X0A X1A X0A X1A Value Min 3.4 238 32 10 0.032 0.032 0.032 12.5 50 25 50 Typ Max 4.2 294 100 31.25 80 20 40 20 31250 31250 31250 Unit MHz Main clock ns kHz Sub clock s MHz CPU MHz Peripheral MHz External bus MHz ns ns ns ns Clock after divided by CAN prescaler CPU Peripheral External bus Clock after divided by CAN prescaler Remarks
* Conditions for measuring the clock timing ratings
tC, tCS
Output pin
X0, X0A X1, X1A
0.8 VCC C = 50 pF
63
MB91460R Series
(2) Clock output timing (VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = - 40 C to + 85 C) Parameter Cycle time SYSCLKSYSCLK SYSCLKSYSCLK Symbol Pin name Condition tCYC tCHCL tCLCH SYSCLK SYSCLK SYSCLK Value Min tCPT 12.5 12.5 Max 108.5 108.5 Unit ns ns ns * Remarks
* : tCYC is the frequency of 1 clock cycle.
tCYC tCHCL tCLCH
VOH
VOH VOL
SYSCLK
(3) Reset input ratings (VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = - 40 C to + 85 C) Parameter INIT input time (at power-on, at return from shutdown mode) INIT input time (other than the above) Symbol Pin name Condition Value Min 8 tINTL INIT 20 s Max Unit
ms
tINTL
INIT
0.2 VCC
64
MB91460R Series
(4) Normal bus access read/write operation (VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter CS0 to CS4 setup CS0 to CS4 hold Symbol tCSLCH tCSDLCH tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address/valid data input time WR0, WR1 delay time Data setup time (WRn rising) Data hold time (WRn rising) WR0, WR1 minimum pulse width RD delay time Data setup time (RD rising) Data hold time (RD rising) RD minimum pulse width AS setup time AS hold time tAVDV tCHWL tCHWH tDSWH tWHDX tWLWH tCHRL tCHRH tDSRH tRHDX tRLRH tASLCH tCHASH SYSCLK A23 to A00 WR0, WR1 A23 to A00 RD A23 to A00 SYSCLK A23 to A00 WR0, WR1 A23 to A00 RD A23 to A00 A23 to A00 D31 to D16 SYSCLK WR0, WR1 D31 to D16 WR0, WR1 D31 to D16 WR0, WR1 WR0, WR1 SYSCLK RD D31 to D16 RD D31 to D16 RD RD SYSCLK AS SYSCLK CS0 to CS4 Pin name Condition Value Min 3 -3 3 3 3 3 3 3 3 tCYC - 3 3 tCYC - 3 20 0 tCYC - 3 3 3 Max tCYC/2 + 6 tCYC/2 + 6 3/2 x tCYC - 15 6 6 6 6 tCYC/2 + 6 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC x the number of cycles added for the delay) to this rating.
65
MB91460R Series
tCYC VOH VOH VOH VOH
SYSCLK
tASLCH tCHASH
AS
VOH VOL tCSLCH tCHCSH VOH
CS0 to CS4
VOL
tASCH
tCHAX VOH VOL tCHRH tRLRH VOL VOH tRHAX
A23 to A00
VOH VOL
tCHRL
RD
tASRL
tDSRH tRHDX tAVDV
VIH
D31 to D16
VIL tCHWL tWLWH
Read
tCHWH
VIH VIL
WR0, WR1
tASWL
VOL
VOH tWHAX tWHDX tDSWH
D31 to D16
VOH VOL
Write
VOH VOL
66
MB91460R Series
(5) Ready input timing (VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter RDY setup time SYSCLK SYSCLK RDY hold time Symbol tRDYS tRDYH Pin name SYSCLK RDY SYSCLK RDY Condition Value Min 10 0 ns Max Unit ns
tCYC VOH VOH VOL
SYSCLK
VOL
tRDYS tRDYH
tRDYS tRDYH
When RDY wait is applied
VOH VOL VOL
VOH
When RDY wait is not applied
VOH VOL
VOH VOL
67
MB91460R Series
(6) Hold timing (VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter BGRNT delay time BGRNT rising from pin floating BGRNT rising from pin valid Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name SYSCLK BGRNT BGRNT Condition Value Min 3 tCYC - 10 tCYC - 10 Max 10 10 tCYC + 10 tCYC + 10 Unit ns ns ns ns
Note : After a BRQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL
tCHBGH VOH tHAHV
BGRNT
tXHAL
VOL
Each pin High impedance
68
MB91460R Series
(7) LIN-UART timing (VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK rising time SCK falling time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tF tR Pin name SCK0 to SCK6 SCK0 to SCK6, SOT0 to SOT6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6 SCK0 to SCK6 SCK0 to SCK6, SOT0 to SOT6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6, SIN0 to SIN6 SCK0 to SCK6 SCK0 to SCK6 External shift clock mode Condition Value Min 5tCYCP - 50 Internal shift clock mode tCYCP + 80 0 tCYCP + 10 3tCYCP 30 tCYCP + 30 Max + 50 150 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
Notes : * Above values are AC characteristics for CLK synchronous mode. * tCYCP is the cycle time of the peripheral clock.
69
MB91460R Series
* Internal shift clock mode
tSCYC
SCK0 to SCK6
VOL tSLOV VOH VOL
VOH
VOL
SOT0 to SOT6
tIVSH VOH VOL
tSHIX VOH VOL
SIN0 to SIN6
* External shift clock mode
tSLSH
tSHSL VOL VOH VOL
SCK0 to SCK6
VOL tSLOV VOH VOL
SOT0 to SOT6
tIVSH VOH VOL
tSHIX VOH VOL
SIN0 to SIN6
70
MB91460R Series
(8) DMA controller timing (VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter DREQ0 input pulse DACK0 delay time DEOP0 delay time IORD delay time IOWR delay time Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCHIRL tCHIRH tCHIWL tCHIWH Pin name DREQ0 DACK0 DEOP0 IORD IOWR Condition Value Min Max 10 10 10 10 10 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns
tCYC
SYSCLK
VOH
VOH
VOH
VOH
tCLDL
tCLDH VOL VOH
DACK0
tCLEL
tCLEH VOH VOL
DEOP0
tCHIRL
tCHIRH VOH
IORD
VOL
tCHIWL
tCHIWH
IOWR
VOL
VOH
tDRWH
DREQ0
VOL
VOH
71
MB91460R Series
(9) Free-run timer clock (VCC3 = 3.0 V to 3.6 V, VCC5 = 4.0 V to 5.5 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter Input pulse width Symbol tTIWH, tTIWL Pin name FRCK0 to FRCK3 Condition Value Min 4tCYCP Max Unit ns
Note : tCYCP is the cycle time of the peripheral clock.
FRCK0 to FRCK3
tTIWH tTIWL
(10) Trigger input timing (VCC3 = 3.0 V to 3.6 V, VCC5 = 4.0 V to 5.5 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter Input capture input trigger A/D converter trigger Symbol tINP tATGX Pin name ICU0 to ICU3 ATG Condition Value Min 5tCYCP 5tCYCP Max Unit ns ns
Note : tCYCP is the cycle time of the peripheral clock.
tATGX, tINP
ICU0 to ICU3, ATG
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MB91460R Series
5. Electrical characteristics for A/D converter
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = -40 C to + 85 C) Parameter Resolution Total error*
1 1
Symbol VOT VFST IAIN VAIN IA
Pin name AN0 to AN15 AN0 to AN15 AN0 to AN15 AVRH AVCC3
Value Min Typ Max 10 3 2.5 1.9
Unit bit LSB LSB LSB
Remarks
Linearity error*
Differential linearity error*1 Zero transition voltage*1 Full transition voltage* Conversion time Analog port input current Analog input voltage Reference voltage Analog power supply current (analog + digital) Analog input equivalent capacity Analog input equivalent resistance Output impedance of analog signal source
1
At AVcc3 = 3.3 V, AVRH = 3.3 V
AVRL-1.5 AVRL + 0.5 AVRL + 2.5 LSB AVRH-1.5 AVRH + 0.5 LSB 1.5 10 AVRH AVCC3 2.5 10 14.7 1.9 1.9 s A V V mA A pF k k Including reference supply 1*
2
AN0 to AN15 AVRH-3.5
AVSS AVSS
IAH*3 Cin Rin Rext AN0 to AN15 AN0 to AN15
*1 : Standard value in the CPU sleep state *2 : Set the peripheral clock and conversion time setting register to set a time equal to or longer than this time. *3 : The current when A/D converter is not operating, or in the CPU stop mode (at VCC3 = AVCC3 = AVRH = 3.3 V).
73
MB91460R Series
(2) Cautions Relating to the A/D Converter The diagram below shows the equivalent circuit of the sampling circuit in the A/D converter. The output impedance of the external circuit connected to the analog input must satisfy the following criteria. * The recommended output impedance for the external circuit is 1.9 k or less. * If an external capacitor is used, remember to consider the capacitive voltage divider effect due to the external capacitor and the internal capacitor in the chip. Accordingly, an external capacitance several thousand times that of the internal capacitance is recommended. * The analog voltage sampling period may be too short if the output impedance of the external circuit is high. In this case, select Rext and Tsamp such that they satisfy the following condition. Rext = Tsamp/ (7 x Cin) - Rin Rext Tsamp Cin Rin : Output impedance of the analog signal source : Sampling time : Equivalent capacitance of analog input : Equivalent resistance of analog input
* Input impedance
Analog input pin Rin:1.9 k (Max) Analog SW
Analog signal source
Rext
Cin:14.7 pF (Max)
A/D converter
Device internal circuit
74
MB91460R Series
Definition of A/D converter terms * Resolution Analog variation that is recognizable by an A/D converter. * Linearity error Deviation between actual conversion characteristics and a straight line connecting zero transition point ("00 0000 0000B" "00 0000 0001B") and full scale transition point ("11 1111 1110B " "11 1111 1111B"). * Differential linearity error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error This error indicates the difference between actual and theoretical values, including the zero transition error/ full scale transition error/linearity error.
Linearity error
3FFH 3FEH {1 LSB' (N - 1) + VOT} 3FDH
Actual conversion characteristics
Differential linearity error
Actual conversion characteristics
(N+1)H
VFST
Digital output
Digital output
(measurement value)
Ideal characteristics
NH
004H 003H 002H 001H
VNT
(measurement value)
(N-1)H
V (N+1) T VNT
(measurement value)
Actual conversion characteristics
(measurement value)
Ideal characteristics
(N-2)H
VOT (measurement value)
AVSS AVRH AVSS
Actual conversion characteristics
AVRH
Analog input
Analog input
Linearity error of digital output N =
VNT - {1LSB' x (N - 1) + VOT} [LSB] 1LSB'
Differential linearity error of digital output N = V (N + 1) T - VNT [LSB] 1LSB' 1LSB = VFST - VOT 1022 [V]
N VOT VFST VNT
: A/D converter digital output value : A voltage at which digital output transits from (000) H to (001) H : A voltage at which digital output transits from (3FE) H to (3FF) H : A voltage at which digital output transitions from (N-1) Hto NH (Continued) 75
MB91460R Series
(Continued) Total error
3FFH 3FEH 1.5 LSB'
Digital output
3FDH
Actual conversion characteristics
{1 LSB' (N - 1) + 0.5 LSB'}
004H
VNT
003H 002H 001H 0.5 LSB' AVSS AVRH
(measurement value) Actual conversion characteristics
Ideal characteristics
Analog input
1LSB' (ideal value) = AVRH - AVSS 1024
[V]
Total error of digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB'
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N + 1) H to NH VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V]
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MB91460R Series
ORDERING INFORMATION
Part number MB91F467RPMC-GSE1 Package 176-pin plastic LQFP (FPT-176P-M07) Remarks Lead-free package
77
MB91460R Series
PACKAGE DIMENSION
176-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.50 mm 24.0 x 24.0 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP (FPT-176P-M07)
26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ
Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
132
89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0~8
0.100.10 (.004.004) (Stand off)
INDEX 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB91460R Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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